Circuit designers use electronic design automation (EDA) tools, a category of computer aided design (CAD) tools, to create a functional circuit design, including a register transfer logic (RTL representation) representation of the functional circuit design, synthesize a “netlist” from the RTL representation, and implement a layout from the netlists. Synthesis of the netlist and implementation of the layout involve simulating the operation of the circuit and determining where cells should be placed and where the interconnects that couple the cells together should be routed. EDA tools allow designers to construct a circuit, simulate its performance, estimate its power consumption and area and predict its yield using a computer and without requiring the costly and lengthy process of fabrication. EDA tools are indispensable for designing modern ICs, particularly very-large-scale integrated circuits (VLSIs). For this reason, EDA tools are in wide use.
One such EDA tool performs timing signoff. Timing signoff is one of the last steps in the IC design process and ensures that signal propagation speed in a newly-designed circuit is such that the circuit will operate as intended. Signals that propagate too slowly through various time domains of an integrated circuit cause setup violations; signals that propagate too quickly through the various time domains cause hold violations. Setup or hold violations frustrate the logic of the circuit and prevent it from performing the job it was designed to do.
Even with EDA tools designed to coordinate the timing in integrated circuits, current design methodologies are limited at the point of clock-tree-synthesis (CTS). Typical design methodologies for integrated circuits with multiple clock domains require the design team provide estimates of clock-insertion delays based on designer knowledge, or use a tool to attempt to minimize the delays on all the clocks. Given the complexity of inter-clock transfers in modern designs and the sheer number of clock domains, it is usually not possible for the design team to understand all the inter-clock transfers that can be impacted by the clock-tree insertion delays. This can result in situations where the design team cannot predict best possible insertion delays, or the tool attempts to build a clock network without analysis as to whether it is optimal, or even realizable under the given set of constraints. Accordingly, problems with the design of the integrated circuit often occur.